1. Field of the Invention
The present invention relates to a data processing apparatus and slave interface mechanism for controlling access to a slave logic unit by a plurality of master logic units.
2. Description of the Prior Art
A data processing apparatus will typically have a number of logic units that are interconnected via a bus, with data being transferable between the logic unit via the bus. To effect such a transfer, a first logic unit may output a transfer request on to the bus, this transfer request being destined for a second logic unit. The second logic unit will then retrieve the transfer request from the bus and perform an appropriate operation in order to process the transfer request. Logic units that are designed to initiate transfer requests can be referred to as “master” logic units, whilst logic units that are designed to be recipients of such transfer requests can be referred to as “slave” logic units.
Such a data processing apparatus is illustrated in FIG. 1, where here it may be considered that the data processing apparatus is in the form of a microcontroller chip. The chip has a number of master logic units connected to a main system bus 200, namely a test controller (referred to hereafter as a Test Interface Controller (TIC)) 100, a Central Processing Unit (CPU) 110 and a Direct Memory Access (DMA) controller 120. Due to the fact that bus signals are shared by the logic units connected to the bus, only one of the master logic units may have access to the system bus at any particular instance in time, and hence an arbiter 130 is provided to control access to the system bus 200 by the various master logic units. When a master logic unit wishes to have access to the system bus 200, it issues a bus request signal to the arbiter 130. If only one bus request signal is received by the arbiter 130 at any particular instance in time, it will grant access to the master logic unit that issued that bus request signal. However if more than one bus request signal is received by the arbiter at any particular instance in time, the arbiter is arranged to apply predetermined priority criteria in order to determine which master logic unit should have access to the system bus 200. Of all of the master logic units requesting access to the bus, the arbiter 130 is arranged to grant access to the master logic unit having the highest priority.
In the FIG. 1 example, it can be seen that there are six slave logic units connected to the main system bus 200, namely a Static Memory Interface (SMI) 140 acting as an interface to external SRAM or ROM, an internal ROM memory 150, an internal RAM memory 160, an SDRAM controller 190 acting as an interface to external SDRAM, and two peripheral bus subsystems 170 and 180. The first peripheral bus subsystem 170 is provided for peripherals that do not require DMA, whilst the second peripheral bus subsystem 180 is provided for peripherals that require DMA. As will be appreciated by those skilled in the art, each peripheral bus subsystem will generally consist of a peripheral bus coupled to the main bus 200 via a bridge, with individual peripheral devices then being connected to the peripheral bus. It will also be appreciated by those skilled in the art that the individual peripheral devices connected to the peripheral bus will be slave logic units, but that the entire peripheral bus subsystem can be considered logically as a single slave logic unit connected to the main bus 200.
One characteristic of the FIG. 1 approach is that it allows every master logic unit to access every slave logic unit in the system via a single bus. However, to support this flexibility, the FIG. 1 architecture uses the arbiter to ensure that, when a master logic unit is granted access to the bus, other master logic units requesting the bus have to wait until the current master logic unit finishes its transfer. It will be appreciated that this is a limiting factor on the processing speed of the data processing apparatus.